1. Field of the Invention
This invention relates to liquid crystal display systems and particularly to systems comprising an array of individually addressable electrodes formed on a semiconductor backplate.
2. Description of the Prior Art
One type of liquid crystal display system comprises a plurality of individually addressable cells arranged in a matrix, with each of the elemental cells of the array operating as a reflective light valve. In the absence of an applied potential, the liquid crystal material is clear and the cell appears dark to an observer. When an electric potential above a threshold level is applied across the liquid crystal material, it scatters the light, much like a piece of frosted glass, and the cell appears white to the observer. The percentage of incident light which is scattered toward the viewing area is proportional to the magnitude of the potential applied to the liquid crystal cell, and, consequently, gray level display presentations may be generated.
In high resolution display systems, a composite presentation is built up from thousands of individually controllable elemental liquid crystal cells, each of which must be updated (the potential across the cell reprogrammed) at a rate sufficiently high to prevent observable flicker in the presentation. This may be accomplished by sandwiching a thin layer of liquid crystal material between a glass plate having a transparent electrode and a backplate having a matrix array of reflective electrodes formed on a semiconductor wafer. The backplate also contains the individual addressing circuitry (field-effect transistor) and electrical storage circuitry (capacitor) disposed contiguous to the reflective liquid crystal contact electrode for each cell, with the reflective electrode forming one element or plate of the capacitor. Each field effect transistor is utilized to address an associated element of the matrix array, and the associated storage capacitor maintains the applied potential across the liquid crystal cell until the information is updated or "refreshed". (Current television industry standards required the update of information every 33 milliseconds.)
A liquid crystal display of the type described hereinabove is disclosed, for example, in U.S. Pat. No. 3,862,360 issued to Dill et al which is assigned to the assignee of the present invention. McGreivy et al in U.S. Pat. No. 4,103,297, also assigned to the assignee of the present invention, presents an improvement upon the device disclosed by Dill in that the individual circuits of the display, formed into an array on the semiconductor backplate, are protected from the known deleterious effect of (even low levels of) illumination upon certain exposed portions such as between the adjacent reflective (metallic) electrodes. McGreivy et al obtain protection from hole-electron generation effects relating to the space charge regions beneath the reflective electrodes and depletion regions adjacent MOSFET sources by combining highly doped, ion-implanted regions immediately under the backplate insulator layer with a reflective electrode geometry which prevents the creation of space charge regions and, hence, harmful inversion layers.
Other regions in which device illumination effects degrade performance and design are associated with the buses which supply video and control data to the individual cell circuits. These orthogonal bus sets, each of which comprises a plurality of parallel conductors, interlie the reflective electrodes, their intersections defining the individual cell areas and borders. The individual reflective electrodes, conductive elements, must maintain a separation distance therebetween to avoid electrical shorting. This leaves the underlying buses exposed to illumination which hitherto has necessitated the fabrication of both sets of buses of material unaffected by illumination, such as polycrystalline silicon (polysilicon) doped for conductivity. A design problem is encountered by a matrix formed of such buses at each intersection thereof caused by the need to maintain electrical insulation between the buses. The solution commonly employed has been to fabricate conductive "underpass" regions at such intersections consisting of highly doped conductive segments of one bus underlying and insulated from the other bus. These regions underlie and extend somewhat beyond the regions of intersection. An insulating layer of oxide separates this doped region from the layer of polysilicon of which both bus sets are formed. Holes are etched in the overlying oxide so that electrical contact is obtained between this highly doped region and one of the two intersecting buses. The "overpassing" polysilicon bus protects the highly doped region from the noise and other undesirable effects otherwise caused by hole-electron generation and ionization within the diffusion which would result from the exposure of the doped region to illumination.
A constraint upon cell size, and, consequently, the video resolution and compactness obtainable by means of the above-described prior art matrix is associated with the existence of the above-described "underpass" regions. Since the two sets of intersecting buses are conductive and formed substantially of one polycrystalline layer, tolerances must be observed to avoid shorting therebetween near the region of intersection (i.e., the discontinuity in the polysilicon portion of the underpassing bus). Such tolerances necessarily leave a small portion of the underlying doped region exposed to illumination and unavoidably result in the introduction of a quantum of illumination noise. Additionally, maintenance of the mechanical integrity of the device in light of presently available fabrication techniques dictates a minimal spacing between any two holes in the oxide layer. The latter consideration is complicated by the fact that an additional oxide hole per cell must be provided for the electrical coupling of the reflective electrode to the remainder of the underlying circuit. In sum, considerations of the above nature, plus the common practice of forming one capacitor plate of a highly doped region of the substrate so that FET and capacitor are side-by-side, have limited the resolution obtainable in present day liquid display panels to a picture cell (or pixel) area of approximately 10.times.10 mils. Inherent in this above-described limitation upon the compactness of cell area, and hence panel size obtainable, is the concomitant inability to mass produce useable panels of such size with efficient and economical present day methods of manufacture, as yield per chip is severely limited.